For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, or gate-all-around devices, such as nanowires, have become more prevalent as device dimensions continue to scale down. Many different techniques have been attempted to reduce parasitic capacitance of such transistors. However, significant improvements are still needed in the area of parasitic capacitance suppression. Also, many different techniques have been attempted to manufacture devices with non-Si channel materials such as SiGe, Ge, and III-V materials. However, significant process improvements are still needed to integrate these materials onto Si wafers.